VLSI Testing and Design for Testability
Edit Page
Report
Scan day: 05 March 2014 UTC
13
Virus safety - good
Description: Computer Engineering Research Center for VLSI Testing and Design for Testability at The University of Texas, Austin
VLSI Testing and Design for Testability VLSI Testing and Design for Testability Research Computer Engineering Research Center The University of Texas at Austin The research emphasis in this area is to develop new techniques for generating high quality tests for very large designs. We believe that the complexity of test generation can be managed only by a hierarchical approach which exploits information about the behavior of the design (included in the behavioral and RTL simulation models developed early in the design cycle). Techniques are being developed to extract useful test information automatically from the high level simulation models and to use this information to develop thorough tests. In cases where the fault coverage is not adequate or where the test length is excessive, modifications are suggested to the behavioral models to improve the testability of the design. Results from formal verification are used to achieve these goals. Target systems include complex processors and ASICs as well as analog and mixed-signal systems.
Size: 1049 chars
Contact Information
Email: —
Phone&Fax: —
Address: —
Extended: —
WEBSITE Info
| Page title: | VLSI Testing and Design for Testability |
| Keywords: | |
| Description: | |
| IP-address: | 128.83.175.2 |