Sheldon B. Akers VLSI Testing Laboratory
Edit Page
Report
Scan day: 08 March 2014 UTC
7
Virus safety - good
Description: Partial scan/BIST insertion, testable core synthesis, FPGA testing, and software testing techniques for hardware validation.
TOPMARGIN=0 LEFTMARGIN=0> This lab is devoted to the study of testing problems in hardware and hardware/software systems. For large hardware and software design projects, it is typical that over 50% of design effort and cost is dedicated to testing and debugging. Our research includes testing for design errors and testing for physical defects occuring during the VLSI manufacturing process. The laboratory is directed by
Size: 429 chars
Contact Information
Email: —
Phone&Fax: —
Address: —
Extended: —
WEBSITE Info
| Page title: | UCI System Test Laboratory |
| Keywords: | test testing hardware software harris reconvergent fanout FPGA covalidation |
| Description: | Information about testing research performed at the University of California Irvine |
| IP-address: | 128.195.1.86 |