Simply RISC
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Description: Designs and supports open-source RISC processors, systems, peripherals; sells S1 Core, a 64-bit Wishbone-compliant CPU Core based on reduced Sun Microsystems OpenSPARC T1 microprocessor. Catania, Italy; Bristol, UK.
Simply RISC - Experimenting with the S1 Core on FPGA Experimenting with the S1 Core on FPGA The FPGA board "Xilinx ML507" on my desk inspired me to try to connect the S1 Core to the Xilinx DDR2 controller using the standard Wishbone bus.
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WEBSITE Info
| Page title: | Simply RISC - Experimenting with the S1 Core on FPGA |
| Keywords: | RISC, risc, simply, srisc, SRISC, verilog, hdl, vhdl, simulator, sparc, SPARC, mips, MIPS, PowerPC, powerpc, PPC, ppc, cache, dma, dmac, ddr, memory, icarus, iverilog, fpga, asic, synthesis, dc, design compiler |
| Description: | Simply RISC designs and supports free/libre open-source RISC processors, systems and peripherals |
| IP-address: | 217.64.195.245 |
WHOIS Info
| NS | Name Server: NS1.TH.SEEWEB.IT Name Server: NS2.TH.SEEWEB.IT |
| WHOIS | Status: ok |
| Date | Creation Date: 30-jan-2006 Expiration Date: 30-jan-2019 |