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John Mashey on RISC/CISC

WARNING: you may want to print this one to read it... (from preceding discussion): :Anyway, it is not a fair comparison. Not by a long stretch. Let's see :how the Nth generation SPARC, MIPS, and 88K's do (assuming they last) :compared to some new design from scratch. Well, there is baggage and there is BAGGAGE. One must be careful to distinguish between ARCHITECTURE and IMPLEMENTATION: a) Architectures persist longer than implementations, especially user-level Instruction-Set Architecture. b) The first member of an architecture family is usually designed with the current implementation constraints in mind, and if you're lucky, software people had some input. c) If you're really lucky, you anticipate 5-10 years of technology trends, and that modifies your idea of the ISA you commit to. d) It's pretty hard to delete anything from an ISA, except where: 1) You can find that NO ONE uses a feature (the 68020 to 68030 deletions mentioned by someone else). 2) You believe that you can trap and emulate the feature "fast enough". i.e., microVAX support for decimal ops, 68040 support for transcendentals. Now, one might claim that the i486 and 68040 are RISC implementations of CISC architectures .... and I think there is some truth to this, but I also think that it can confuse things badly: Anyone who has studied the history of computer design knows that high-performance designs have used many of the same techniques for years, for all of the natural reasons, that is: a) They use as much pipelining as they can, in some cases, if this means a high gate-count, then so be it. b) They use caches (separate I & D if convenient). c) They use hardware, not micro-code for the simpler operations. (For instance, look at the evolution of the S/360 products. Recall that the 360/85 used caches, back around 1969, and within a few years, so did any mainframe or supermini.) So, what difference is there among machines if similar implementation ideas are used? A: there is a very specific set of characte

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